Placing ferroelectric material between the plates of a capacitor on a semiconductor substrate causes the capacitor to exhibit a memory effect in the form of charge polarization between the plates of the capacitor. In effect, when the capacitor is charged with the field lines running in one direction across the capacitor plates, a residual charge polarization remains after the charge is removed from the capacitor plates. If an opposite charge is placed on the capacitor plates, an opposite residual polarization remains. A plot of the applied field voltage (E) across the plates of the capacitor against the polarization (P) of the ferroelectric material between the plates of the capacitor exhibits a classic hysteresis curve as shown in FIG. 1. This type of hysteresis response of ferroelectric material between the plates of the capacitor manufactured on a semiconductor die as known in the art and is described in U.S. Pat. No. 4,873,664 to Eaton Jr., which is incorporated herein by reference.
Using ferroelectric material in the manufacture of capacitors for use in the cells of memory arrays is also known in the art. By applying a coercive voltage across the plates of the ferroelectric capacitor to produce one polarization or another, the residual polarization stores a nonvolatile 1 or 0 in the cell. If a ferroelectric capacitor has zero volts applied across its plates, it may be polarized as indicated by either point A or point D in FIG. 1. Assuming that the polarization is at point A, if a positive voltage is applied across the capacitor which is greater than the "coercive voltage" indicated by line B, then the capacitor will conduct current and move to a new polarization at point C. When the voltage across the capacitor returns to zero, the polarization will remain the same and move to point D. If a positive voltage is applied across the capacitor when it is polarized at point D, the capacitor will not conduct current, but will move to point C. It can be seen that a negative potential can be used to change the polarization of a capacitor from point D to point A. Therefore, points A and D can represent two logic states occurring when zero volts are applied to the capacitor and which depend upon the history of voltage applied to the capacitor.
The reading of the polarization of the ferroelectric capacitor can be a destructive read in which a pulse is applied to the ferroelectric capacitor and the amount of resultant charge is either low if the pulse polarity agreed with the previous memorization polarity, or the resultant charge is higher if the charge polarity placed on the capacitor is of the opposite polarity last placed across the plates of the capacitor. This minute difference between an agreeable charge and an opposite charge can be measured to determine what the previous polarization on the ferroelectric capacitor was as it was last written. If a large charge results from reading a memory cell, the memory cell polarization will move from one state to the other state, for example point A to Point D. Thus, the data read from the memory cell must be restored.
The fact that the ferroelectric capacitors require a destructive read to determine the last polarization, and the fact that the resultant charge differences of the ferroelectric capacitor between an agreeable applied pulse and an opposite applied pulse make the technique of reading and writing ferroelectric memories a difficult task. The benefit of having a nonvolatile memory in which stored data remains without any battery backup or other external application of power is of great use in the computer and control industries. However, for any such nonvolatile memories to be of any use, the memories must be of a high enough density and must have a fast enough response time to make them commercially more attractive than battery backed up DRAM, mechanical disk storage and other types of nonvolatile storage.
One of the shortcomings of the prior art is the fact that the ferroelectric capacitors age through use, producing distinctly nonlinear hysteresis curves such as that shown in FIG. 2. Thus, it becomes increasingly difficult to determine the correct polarization of the cells as they age. For example, if a memory cell fabricated as a ferroelectric capacitor is polarized at point A in FIG. 2, a positive voltage greater than the coercive voltage B will move the polarization of the cell to point C. When moving from point A to point C the capacitor will conduct current. When reading a memory cell having polarity of point D using a positive voltage, however, a current is also conducted as the polarity moves to point C. The differences between the resultant currents of the two different states of the capacitor, therefore, becomes smaller as the capacitor ages. It will be appreciated that reading a memory cell having a hysteresis curve of FIG. 2 will be more difficult than reading a memory cell having an ideal hysteresis curve of FIG. 1.
Another shortcoming of the prior art is the inability to produce high density ferroelectric memories having high operating speeds comparable to that of DRAM storage devices. Along these lines, the aforementioned Eaton Jr. patent describes the application of ferroelectric capacitors to high density memory storage, as shown in FIG. 3. In this arrangement, each memory storage cell comprises a pair of ferroelectric capacitors and a pair of access transistor. One plate of the pair of ferroelectric capacitors is connected to a plate line, while the other plates of the ferroelectric capacitor are connected through access transistors to separate bit lines. In operation, a momentary voltage pulse is placed on the ferroelectric capacitors between the bit lines and the plate line to polarize the ferroelectric material of the two ferroelectric capacitors, resulting in a polarization of one direction for one capacitor and an opposite polarization for the second ferroelectric capacitor.
Eaton Jr. takes this concept a step further by using a regular array of ferroelectric capacitors, whereby each cell contains two ferroelectric capacitors and two access transistors. The ferroelectric capacitors within each memory cell receives complementary input signals such that the ferroelectric capacitors are polarized in opposite states to indicate a 1 or a 0. When the pairs of capacitors for each cell are read, a resulting voltage on the bit lines, which result from applying a pulse on a plate line, is compared using a differential sense amplifier to compare the voltages on the bit lines and thus determine the polarity on the ferroelectric capacitors within the cell.
The disadvantage of the above approach is that Eaton Jr. requires that each cell contain at least two transistors and two ferroelectric capacitors. This approach takes up a large area of the chip for implementation, which limits the overall density of a memory array.
An improvement on the Eaton Jr. et al. approach is found in U.S. patent application No. 08/175,923 entitled "REFERENCE CIRCUIT FOR A NONVOLATILE FERROELECTRIC MEMORY" to Lowry et al. This patent application is assigned to the same assignee as the present patent application. It is not prior art. This improvement for ferroelectric memory designs from Lowry et al. describes an array of memory cells in which each cell comprises a single ferroelectric capacitor and a single access transistor. The cells are arranged in a regular array such that common word lines and common plate lines are used to access rows of ferroelectric capacitor cells. The Lowry et al. patent application describes a folded bit line architecture in which bit lines for adjacent columns have staggered cells, such that a word line (WL) from one row does not activate memory cells 80 on adjacent bit lines, as seen in FIG. 4. It will be appreciated that the plate lines PL0 and PL1 can be combined as one common plate. In the Lowry et al. patent application, the result is an active bit line (BL) for one column, and an inactive bit line for an adjacent column when the word line and plate lines are activated for reading or writing a particular ferroelectric memory cell. With an adjacent inactive bit line, the unused bit line is available for attachment to a single-ended reference circuit 90 using a reference decoder 92. The single-ended reference circuit of Lowry et al. allows for placing a highly accurate voltage on the adjacent unused bit line, which can be used by the sense amplifier 94 to compare to any active bit line to determine the state of the ferroelectric capacitor, when the plate line is pulsed. U.S. patent application No. 08/175,923 to Lowry et al. is hereby incorporated by reference.
Integrated memory circuits which use ferroelectric memory cells are susceptible to loses of data during read and write operations. When reading a ferroelectric memory cell located at a memory address, the data stored on the cell can be lost and must be replaced before accessing a new memory address. Additionally, during a write operation where the data stored on the memory cell is to be replaced with the opposite logic state, several steps must be completed to store the new data. During these write operation steps, the memory address must not change, or the new data will be lost. Still lacking in the industry is a ferroelectric memory array using a RAM architecture which insures that data will not be lost during an asynchronous memory cell access operation.